Statistical Modeling of Device Mismatch MOS Integrated Circuits for Analog

A generalized parameter-level statistical MOS model, called SMOS, capable of generating statistically significant model decks from intraand inter-die parameters statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. This will ultimately lead to computer-aided optimization of both circuit and layout design of analog integrated circuits. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms.